Result Details:

Result Details
Worst VIH(See image)Number of burst(s) measured1NumOfMeas4.000PUTDQ0PUT SrcChannel 3Supporting PinDQS0,/DQS0Supporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Min (VrefDQ_Volt+AcLevels_DQ_Volt)925.000000000mV

Trial 1

Trial 1: Worst VIH

VIH.DQ(DC) Reference: JEDEC Standard No. 79-3F, Table 24 (Vref=0.75; VDD=1.50)

Test Summary: Pass Test Description: DC Input Logic High
Pass Limits:[VrefDQ_Volt+DcLevels_VoltV to VDD_VoltV]VIH.DQ(DC)926.805100000mV

Result Details:

Trial 1

Trial 1: Worst VIH

VIL.DQ(AC) Reference: JEDEC Standard No. 79-3F, Table 24 (Vref=0.75)

Test Summary: Pass Test Description: AC Input Logic Low
Pass Limits:<= VrefDQ_Volt-AcLevels_DQ_VoltVVIL.DQ(AC)563.000600000mV

Result Details:

Result Details
Worst VIL(See image)Number of burst(s) measured1NumOfMeas3.000PUTDQ0PUT SrcChannel 3Supporting PinDQS0,/DQS0Supporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Max (VrefDQ_Volt-AcLevels_DQ_Volt)575.000000000mV

Trial 1

Trial 1: Worst VIL

VIL.DQ(DC) Reference: JEDEC Standard No. 79-3F, Table 24 (Vref=0.75; VSS=0.00)

Test Summary: Pass Test Description: DC Input Logic Low
Pass Limits:[0.000000000000V to VrefDQ_Volt-DcLevels_VoltV]VIL.DQ(DC)563.000600000mV

Result Details:

Trial 1

Trial 1: Worst VIL

VSEH(Strobe) Reference: JEDEC Standard No. 79-3F, Table 27 (VDDQ=1.5)

Test Summary: FAIL Test Description: Single-ended High Level Voltage for Strobes
Pass Limits:>= VDD_Volt/2 + 0.175VVSEH-9.0000000000000E36V

Result Details:

Result Details
Worst VSEH(See image)Number of burst(s) measured-9.0000000000000E36NumOfMeas-9.0000000000000E36Min-9.000000e+036Max-9.000000e+036PUTDQS0,GndPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Min (VDD_Volt/2 + 0.175)925.000000000mV

Trial 1

Trial 1: Worst VSEH

VSEL(Strobe) Reference: JEDEC Standard No. 79-3F, Table 27 (VDDQ=1.5)

Test Summary: FAIL Test Description: Single-ended Low Level Voltage for Strobes
Pass Limits:<= VDD_Volt/2 - 0.175VVSEL9.0000000000000E36V

Result Details:

Result Details
Worst VSEL(See image)Number of burst(s) measured9.0000000000000E36NumOfMeas9.0000000000000E36Min9.000000e+036Max9.000000e+036PUTDQS0,GndPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Max (VDD_Volt/2 - 0.175)575.000000000mV

Trial 1

Trial 1: Worst VSEL

VSEH(Clock) Reference: JEDEC Standard No. 79-3F, Table 27 (VDDQ=1.5)

Test Summary: Pass Test Description: Single-ended High Level Voltage
Pass Limits:>= VDD_Volt/2 + 0.175VVSEH(AC)1.108940000000V

Result Details:

Result Details
Worst VSEH(See image)NumOfMeas10.000Min1.108940e+000Max1.200400e+000PUTCK0PUT SrcChannel 1PassLimit Min (VDD_Volt/2 + 0.175)925.000000000mV

Trial 1

Trial 1: Worst VSEH

VSEL(Clock) Reference: JEDEC Standard No. 79-3F, Table 27 (VDDQ=1.5)

Test Summary: Pass Test Description: Single-ended Low Level Voltage
Pass Limits:<= VDD_Volt/2 - 0.175VVSEL-1.029060000000V

Result Details:

Result Details
Worst VSEL(See image)NumOfMeas10.000Min-1.149400e+000Max-1.029060e+000PUTCK0PUT SrcChannel 1PassLimit Max (VDD_Volt/2 - 0.175)575.000000000mV

Trial 1

Trial 1: Worst VSEL

VOH(AC) Reference: JEDEC Standard No. 79-3F, Table 30 (VTT=0.75; VDDQ=1.50)

Test Summary: Pass Test Description: AC Output Logic High
Pass Limits:>= VTT_Volt+0.1*VDDQ_VoltVVOH(AC)1.241860000000V

Result Details:

Result Details
Worst VOH(See image)NumOfMeas4.000PUTDQ0PUT SrcChannel 3Supporting PinDQS0,/DQS0Supporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Min (VTT_Volt+0.1*VDDQ_Volt)900.000000000mV

Trial 1

Trial 1: Worst VOH

VOH(DC) Reference: JEDEC Standard No. 79-3F, Table 30 (VDDQ=1.50)

Test Summary: Pass Test Description: DC Output Logic High
Pass Limits:>= 0.8*VDDQ_VoltVVOH(DC)1.241860000000V

Result Details:

Trial 1

Trial 1: Worst VOH

VOL(AC) Reference: JEDEC Standard No. 79-3F, Table 30 (VTT=0.75; VDDQ=1.50)

Test Summary: Pass Test Description: AC Output Logic Low
Pass Limits:<= VTT_Volt-0.1*VDDQ_VoltVVOL(AC)294.670000000mV

Result Details:

Result Details
Worst VOL(See image)NumOfMeas3.000PUTDQ0PUT SrcChannel 3Supporting PinDQS0,/DQS0Supporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Max (VTT_Volt-0.1*VDDQ_Volt)600.000000000mV

Trial 1

Trial 1: Worst VOL

VOL(DC) Reference: JEDEC Standard No. 79-3F, Table 30 (VDDQ=1.50)

Test Summary: Pass Test Description: DC Output Logic Low
Pass Limits:<= 0.2*VDDQ_VoltVVOL(DC)294.670000000mV

Result Details:

Trial 1

Trial 1: Worst VOL

SRQseR Reference: JEDEC Standard No. 79-3F, Table 33

Test Summary: Pass Test Description: Output signal minimum rising slew rate
Pass Limits:[2.500000000000V/ns to 5.000000000000V/ns]SRQseR2.892874000000V/ns

Result Details:

Result Details
Worst SRQseR(See image)Number of burst(s) measured1NumOfMeas4.000SRQSeR_time104psVref750mVVoh_ac900mVVol_ac600mVPUTDQ0PUT SrcChannel 3Supporting PinDQS0,/DQS0Supporting Pin SrcChannel 2Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQseR

SRQseF Reference: JEDEC Standard No. 79-3F, Table 33

Test Summary: Pass Test Description: Output signal minimum falling slew rate
Pass Limits:[2.500000000000V/ns to 5.000000000000V/ns]SRQseF2.940383000000V/ns

Result Details:

Result Details
Worst SRQseF(See image)Number of burst(s) measured1NumOfMeas3.000SRQSeF_time102psVref750mVVoh_ac900mVVol_ac600mVPUTDQ0PUT SrcChannel 3Supporting PinDQS0,/DQS0Supporting Pin SrcChannel 2Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQseF

Overshoot amplitude (Clock, Data, Strobe, Mask) Reference: JEDEC Standard No. 79-3F, Table 37

Test Summary: Pass Test Description: Peak amplitude of AC overshoot
Pass Limits:<= 400.000000000mVOvershoot amplitude (Clock, Data, Strobe, Mask)-204.600000000mV

Result Details:

Result Details
Overshoot Width0.0000000000000sOvershoot Reference1.500VPUTDQ0PUT SrcChannel 3Overshoot Amplitude(See image)

Trial 1

Trial 1: Overshoot Amplitude

Overshoot area (Clock, Data, Strobe, Mask) Reference: JEDEC Standard No. 79-3F, Table 37

Test Summary: Pass Test Description: OverShoot area above VDDQ
Pass Limits:<= 190.000000000mV-nsOvershoot Area (Address, Control)0.000000000000V-ns

Result Details:

Result Details
Overshoot amplitude-205mVOvershoot Width0.0000000000000sOvershoot Reference1.500VPUTDQ0PUT SrcChannel 3Overshoot Area(See image)

Trial 1

Trial 1: Overshoot Area

Undershoot amplitude (Clock, Data, Strobe, Mask) Reference: JEDEC Standard No. 79-3F, Table 37

Test Summary: Pass Test Description: Peak amplitude of AC undershoot
Pass Limits:<= 400.000000000mVUndershoot amplitude (Clock, Data, Strobe, Mask)-258.790000000mV

Result Details:

Result Details
Undershoot Width0.0000000000000sUndershoot Reference0.000VPUTDQ0PUT SrcChannel 3Undershoot Amplitude(See image)

Trial 1

Trial 1: Undershoot Amplitude

Undershoot area (Clock, Data, Strobe, Mask) Reference: JEDEC Standard No. 79-3F, Table 37

Test Summary: Pass Test Description: UnderShoot area below VSSQ
Pass Limits:<= 190.000000000mV-nsUndershoot Area (Clock, Data, Strobe, Mask)0.000000000000V-ns

Result Details:

Result Details
Undershoot Amplitude-259mVUndershoot Width0.0000000000000sUndershoot Reference0.000VPUTDQ0PUT SrcChannel 3Undershoot Area(See image)

Trial 1

Trial 1: Undershoot Area

VIHdiff.CK(AC) Reference: JEDEC Standard No. 79-3F, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic High Voltage
Pass Limits:>= 2*(VIHAC_CA_Volt-VrefCA_Volt)VVIHdiff(AC)481.750000000mV

Result Details:

Result Details
Worst VIH(See image)NumOfMeas10.000Min4.817500e-001Max5.082000e-001PUTCK0,/CK0PUT SrcChannel 1PassLimit Min (2*(VIHAC_CA_Volt-VrefCA_Volt))350.000000000mV

Trial 1

Trial 1: Worst VIH

VILdiff.CK(AC) Reference: JEDEC Standard No. 79-3F, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic Low Voltage
Pass Limits:<= 2*(VILAC_CA_Volt-VrefCA_Volt)VVILdiff(AC)-544.580000000mV

Result Details:

Result Details
Worst VIL(See image)NumOfMeas10.000Min-5.874700e-001Max-5.445800e-001PUTCK0,/CK0PUT SrcChannel 1PassLimit Max (2*(VILAC_CA_Volt-VrefCA_Volt))-350.000000000mV

Trial 1

Trial 1: Worst VIL

VIHdiff.DQS(AC) Reference: JEDEC Standard No. 79-3F, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic High Voltage
Pass Limits:>= 2*(VIHAC_DQ_Volt-VrefDQ_Volt)VVIHdiff(AC)452.890000000mV

Result Details:

Result Details
Worst VIHDiff(See image)NumOfMeas2.000Min4.528900e-001Max4.544600e-001PUTDQS0,/DQS0PUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Min (2*(VIHAC_DQ_Volt-VrefDQ_Volt))350.000000000mV

Trial 1

Trial 1: Worst VIHDiff

VILdiff.DQS(AC) Reference: JEDEC Standard No. 79-3F, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic Low Voltage
Pass Limits:<= 2*(VILAC_DQ_Volt-VrefDQ_Volt)VVILdiff(AC)-401.460000000mV

Result Details:

Result Details
Worst VILDiff(See image)NumOfMeas1.000Min-4.014600e-001Max-4.014600e-001PUTDQS0,/DQS0PUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Max (2*(VILAC_DQ_Volt-VrefDQ_Volt))-350.000000000mV

Trial 1

Trial 1: Worst VILDiff

VIX Reference: JEDEC Standard No. 79-3F, Table 28

Test Summary: FAIL Test Description: AC differential input cross point voltage
Pass Limits:[-150.000000000mV to 150.000000000mV]VIX9.0000000000000E36V

Result Details:

Result Details
Worst VIX(See image)Number of burst(s) measured9.0000000000000E36NumOfMeas9.0000000000000E36PUTDQS0,/DQS0PUT(+) SrcChannel 2PUT(-) SrcChannel 3Supporting PinDQ0Supporting Pin SrcChannel 4

Trial 1

Trial 1: Worst VIX

VOHdiff(AC) Reference: JEDEC Standard No. 79-3F, Table 31(VDDQ=1.50)

Test Summary: Pass Test Description: Differential AC Output Logic High Voltage
Pass Limits:>= 0.2*VDDQ_VoltVVOHdiff(AC)779.910000000mV

Result Details:

Result Details
Worst VOHDiff(See image)NumOfMeas4.000Min7.799100e-001Max8.307400e-001PUTDQS0,/DQS0PUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Min (0.2*VDDQ_Volt)300.000000000mV

Trial 1

Trial 1: Worst VOHDiff

VOLdiff(AC) Reference: JEDEC Standard No. 79-3F, Table 31(VDDQ=1.50)

Test Summary: Pass Test Description: Differential AC Output Logic Low Voltage
Pass Limits:<= -0.2*VDDQ_VoltVVOLdiff(AC)-779.740000000mV

Result Details:

Result Details
Worst VOLDiff(See image)NumOfMeas3.000Min-8.660000e-001Max-7.797400e-001PUTDQS0,/DQS0PUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Max (-0.2*VDDQ_Volt)-300.000000000mV

Trial 1

Trial 1: Worst VOLDiff

SRQdiffR Reference: JEDEC Standard No. 79-3F, Table 35

Test Summary: Pass Test Description: Differential Output Rising Slew Rate
Pass Limits:[5.000000000000V/ns to 10.000000000000V/ns]SRQdiffR5.090149000000V/ns

Result Details:

Result Details
Worst SRQdiffR(See image)Number of burst(s) measured1NumOfMeas4.000SRQdiffR_time118psMin5.090149000000V/nsMax5.207007000000V/nsVOHdiff_ac300mVVOLdiff_ac-300mVPUTDQS0,/DQS0PUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQdiffR

SRQdiffF Reference: JEDEC Standard No. 79-3F, Table 35

Test Summary: Pass Test Description: Differential Output Falling Slew Rate
Pass Limits:[5.000000000000V/ns to 10.000000000000V/ns]SRQdiffF5.235437000000V/ns

Result Details:

Result Details
Worst SRQdiffF(See image)Number of burst(s) measured1NumOfMeas4.000SRQdiffF_time115psMin5.235437000000V/nsMax5.469555000000V/nsVOHdiff_ac300mVVOLdiff_ac-300mVPUTDQS0,/DQS0PUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQdiffF

tDS(base) Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQ and DM input setup time - Differential
Pass Limits:>= tDS_Limit_minstDS330ps

Result Details:

Result Details
Worst tDS(See image)Number of burst(s) measured1.000000e+000NumOfMeas32.000PassLimit Min (tDS_Limit_min)25psCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min330psMax414psMean367psStdev22ps

Trial 1

Trial 1: Worst tDS

tDH(base) Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQ and DM input hold time - Differential
Pass Limits:>= tDH_Limit_minstDH380ps

Result Details:

Result Details
Worst tDH(See image)Number of burst(s) measured1.000000e+000NumOfMeas32.000PassLimit Min (tDH_Limit_min)100psCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min380psMax477psMean431psStdev23ps

Trial 1

Trial 1: Worst tDH

tDS-Diff(derate) Reference: JEDEC Standard No. 79-3F, Table 76, Table77 and Table 78

Test Summary: Pass Test Description: DQ and DM input setup time - Differential
Pass Limits:>= tDSDiff_DeratedLimit_MinstDS330ps

Result Details:

Result Details
Worst tDSDiffDerate(See image)Mean Slewrate for DQ signal1.919374000000V/nsMean Slewrate for DQS signal3.974511000000V/nsBase limit value2.500000e-011Derated limit value8.33236790068948E-11Number of burst(s) measured1.000000e+000NumOfMeas32.000PassLimit Min (tDSDiff_DeratedLimit_Min)108psDerated Limit MethodNominal methodCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min330psMax414psMean367psStdev22ps

Trial 1

Trial 1: Worst tDSDiffDerate

tDH-Diff(derate) Reference: JEDEC Standard No. 79-3F, Table 76, Table77 and Table 78

Test Summary: Pass Test Description: DQ and DM input hold time - Differential
Pass Limits:>= tDHDiff_DeratedLimit_MinstDH380ps

Result Details:

Result Details
Worst tDHDiffDerate(See image)Mean Slewrate for DQ signal2.116816000000V/nsMean Slewrate for DQS signal3.970084000000V/nsBase limit value1.000000e-010Derated limit valueN/ANumber of burst(s) measured1.000000e+000NumOfMeas32.000PassLimit Min (tDHDiff_DeratedLimit_Min)100psDerated Limit MethodNominal methodCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min380psMax477psMean431psStdev23ps

Trial 1

Trial 1: Worst tDHDiffDerate

tDIPW Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQ and DM input pulse width
Pass Limits:>= 490pstDIPW892ps

Result Details:

Result Details
Worst tDIPW(See image)Number of burst(s) measured1.000000e+000NumOfMeas31.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min892psMax4.693nsMean1.632nsStdev1.169ns

Trial 1

Trial 1: Worst tDIPW

tVAC(Data) Reference: N/A

Test Summary: Info Test Description: tVAC(Data)
Pass Limits:Info OnlytVAC(Data)721.1ps

Result Details:

Result Details
WorsttVAC_DQ(See image)Number of burst(s) measured1NumOfMeas31.000NotePlease refer to the JEDEC specification for actual limit.Nominal Slew Rate1.961433e+000V/nsCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIH(AC)(no value)VIL(AC)(no value)Sampling Points(no value)Min721psMax4.512nsMean1.460nsStdev1.172ns

Trial 1

Trial 1: WorsttVAC_DQ

tWPRE Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: Write preamble
Pass Limits:>= 900.000000000mtCKtWPRE1.139028000000tCK

Result Details:

Result Details
tWPRE(See image)tWPRE(s)2.137nsNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min1.139028000000tCKMax1.139028000000tCKMean1.139028000000tCKStdev0.000000000000tCK

Trial 1

Trial 1: tWPRE

tWPST Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: Write postamble
Pass Limits:>= 300.0000000000mtCKtWPST434.4140000000mtCK

Result Details:

Result Details
tWPST(See image)tWPST(s)815psNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min434.414000000mtCKMax434.414000000mtCKMean434.414000000mtCKStdev0.000000000000tCK

Trial 1

Trial 1: tWPST

tDQSS Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS latching transition to associated clock edge
Pass Limits:[-250.000000000mtCK to 250.000000000mtCK]tDQSS89.875980000mtCK

Result Details:

Result Details
Worst tDQSS_DDR3(See image)tDQSS(s)169psNumber of burst(s) measured1.000000e+000NumOfMeas28.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min37.056320000mtCKMax89.875980000mtCKMean59.768380000mtCKStdev13.696150000mtCK

Trial 1

Trial 1: Worst tDQSS_DDR3

tDSS Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS falling edge to CK setup time
Pass Limits:>= 200.000000000mtCKtDSS535.684800000mtCK

Result Details:

Result Details
Worst tDSS(See image)tDSS(s)1.005nsNumber of burst(s) measured1.000000e+000NumOfMeas28.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min535.684800000mtCKMax586.323200000mtCKMean557.826900000mtCKStdev13.233050000mtCK

Trial 1

Trial 1: Worst tDSS

tDSH Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS falling edge hold time from CK
Pass Limits:>= 200.000000000mtCKtDSH411.053700000mtCK

Result Details:

Result Details
Worst tDSH(See image)tDSH(s)771psNumber of burst(s) measured1.000000e+000NumOfMeas28.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min411.053700000mtCKMax463.526800000mtCKMean442.172500000mtCKStdev13.932650000mtCK

Trial 1

Trial 1: Worst tDSH

tDQSL Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS input low pulse width
Pass Limits:[450.000000000mtCK to 550.000000000mtCK]tDQSL493.697600000mtCK

Result Details:

Result Details
Worst tDQSL(See image)tDQSL(s)926psNumber of burst(s) measured1.000000e+000NumOfMeas27.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min493.697600000mtCKMax501.679100000mtCKMean497.411400000mtCKStdev1.824629000mtCK

Trial 1

Trial 1: Worst tDQSL

tDQSH Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS input high pulse width
Pass Limits:[450.000000000mtCK to 550.000000000mtCK]tDQSH505.511600000mtCK

Result Details:

Result Details
Worst tDQSH(See image)tDQSH(s)948psNumber of burst(s) measured1.000000e+000NumOfMeas28.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min498.726700000mtCKMax505.511600000mtCKMean501.940900000mtCKStdev1.760705000mtCK

Trial 1

Trial 1: Worst tDQSH

tDQSQ Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS-DQ skew for DQS and associated DQ signals
Pass Limits:<= 150pstDQSQ45ps

Result Details:

Result Details
Worst tDQSQ(See image)Number of burst(s) measured1.000000e+000NumOfMeas13.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min-20psMax45psMean21psStdev18ps

Trial 1

Trial 1: Worst tDQSQ

tQH Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQ/DQS output hold time from DQS
Pass Limits:>= 380.000000000mtCKtQH467.170200000mtCK

Result Details:

Result Details
Worst tQH(See image)Number of burst(s) measured1.000000e+000NumOfMeas13.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min467.170200000mtCKMax539.820000000mtCKMean506.509100000mtCKStdev23.412070000mtCK

Trial 1

Trial 1: Worst tQH

tLZDQ Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQ low-impedance time from CK,/CK
Pass Limits:[-600.0ps to 300.0ps]tLZDQ73.3ps

Result Details:

Result Details
tLZDQ(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3Sampling Points (Pts)2000000Min73.3psMax73.3psMean73.3psStdev0.0000000000000s

Trial 1

Trial 1: tLZDQ

tHZDQ Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQ out high-impedance time from CK,/CK
Pass Limits:<= 300.0pstHZDQ111.7ps

Result Details:

Result Details
tHZDQ(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_Src3tDQSCK Delay (cycle)Not In UseSampling Points (Pts)2000000Min111.7psMax111.7psMean111.7psStdev0.0000000000000s

Trial 1

Trial 1: tHZDQ

tRPRE Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: Read preamble
Pass Limits:[900.000000000mtCK to 1.480000000000tCK]tRPRE1.133045000000tCK

Result Details:

Result Details
tRPRE(See image)tRPRE(s)2.126nsNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min1.133045000000tCKMax1.133045000000tCKMean1.133045000000tCKStdev0.000000000000tCK

Trial 1

Trial 1: tRPRE

tRPST Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: Read postamble
Pass Limits:[300.0000000000mtCK to 940.0000000000mtCK]tRPST424.7213000000mtCK

Result Details:

Result Details
tRPST(See image)tRPST(s)797psNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min424.721300000mtCKMax424.721300000mtCKMean424.721300000mtCKStdev0.000000000000tCK

Trial 1

Trial 1: tRPST

tDQSCK Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS output access time from CK,/CK
Pass Limits:[-300ps to 300ps]tDQSCK251ps

Result Details:

Result Details
WorsttDQSCK(See image)Number of burst(s) measured1.000000e+000NumOfMeas12.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3Sampling Points (Pts)2000000Min147psMax251psMean203psStdev32ps

Trial 1

Trial 1: WorsttDQSCK

tDVAC(Clock) Reference: N/A

Test Summary: Info Test Description: tDVAC(Clock)
Pass Limits:Info OnlytDVAC(Clock)349.9ps

Result Details:

Result Details
WorsttDVAC_Clock(See image)NotePlease refer to the JEDEC specification for actual limit.Min3.499333e-010sMax5.300662e-010sNumOfMeas1.333320e+005Differential Slew Rate2.335760e+000V/nsCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIHdiff(AC)0.35VILdiff(AC)-0.35Sampling Points2000000

Trial 1

Trial 1: WorsttDVAC_Clock

tLZDQS Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS low-impedance time from CK,/CK
Pass Limits:[-600.0ps to 300.0ps]tLZDQS8.9ps

Result Details:

Result Details
tLZDQS(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3Sampling Points (Pts)2000000Min8.9psMax8.9psMean8.9psStdev0.0000000000000s

Trial 1

Trial 1: tLZDQS

tQSH Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS output high time
Pass Limits:>= 380.0000000000mtCKtQSH488.9755000000mtCK

Result Details:

Result Details
Worst tQSH(See image)Number of burst(s) measured1.000000e+000NumOfMeas12.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min488.975500000mtCKMax526.316900000mtCKMean510.369000000mtCKStdev12.629590000mtCK

Trial 1

Trial 1: Worst tQSH

tQSL Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: DQS output low time
Pass Limits:>= 380.0000000000mtCKtQSL472.4601000000mtCK

Result Details:

Result Details
Worst tQSL(See image)Number of burst(s) measured1.000000e+000NumOfMeas11.000CH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min472.460100000mtCKMax508.650900000mtCKMean487.770900000mtCKStdev11.751550000mtCK

Trial 1

Trial 1: Worst tQSL

tDVAC(Strobe) Reference: N/A

Test Summary: Info Test Description: tDVAC(Strobe)
Pass Limits:Info OnlytDVAC(Strobe)746.9ps

Result Details:

Result Details
WorsttDVAC_DQS(See image)Number of burst(s) measured1NumOfMeas55.000NotePlease refer to the JEDEC specification for actual limit.Differential Slew Rate3.788151e+000V/nsCH1_PUTClockCH1_SrcCK0,/CK0CH2_PUTStrobeCH2_SrcDQS0,/DQS0CH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIHdiff(AC)0.35VILdiff(AC)-0.35Sampling Points2000000Min747psMax768psMean757psStdev5ps

Trial 1

Trial 1: WorsttDVAC_DQS

tjit(CC) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tjit(CC) Rising Edge Measurements
Pass Limits:[-180ps to 180ps]tjitCC Rising-141ps

Result Details:

Result Details
Min-141.257psMax122.926psAbs. Diff264.183psAverage3.439fsPeriods13.339000kMeasurements13.338000kWaveform SrcChannel 1tWorstCaseN/A

Next

tCK(avg) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 63 (CL=8, CWL=6)

Test Summary: FAIL Test Description: tCK(avg) Rising Edge Measurements
Pass Limits:[1.875ns to 2.500ns]tCKavg Rising1.874ns

Result Details:

Result Details
Min1.874nsMax1.876nsAbs. Diff1.186psAverage1.875nsPeriods13.339000kMeasurements13.140000kWaveform SrcChannel 1tWorstCaseN/A

Next

tjit(per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: FAIL Test Description: tjit(per) Rising Edge Measurements
Pass Limits:[-90ps to 90ps]tjitper Rising92ps

Result Details:

Result Details
Min-63.837psMax91.953psAbs. Diff155.790psAverage0.000000000000sPeriods13.339000kMeasurements2.628000000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(2per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(2per) Rising Edge Measurements
Pass Limits:[-132ps to 132ps]terr2per Rising-91ps

Result Details:

Result Details
Min-90.820psMax89.310psAbs. Diff180.129psAverage0.0000000000000sPeriods13.339000kMeasurements2.614860000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(3per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(3per) Rising Edge Measurements
Pass Limits:[-157ps to 157ps]terr3per Rising-98ps

Result Details:

Result Details
Min-98.058psMax74.840psAbs. Diff172.898psAverage0.0000000000000sPeriods13.339000kMeasurements2.601720000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(4per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(4per) Rising Edge Measurements
Pass Limits:[-175ps to 175ps]terr4per Rising-84ps

Result Details:

Result Details
Min-83.866psMax82.121psAbs. Diff165.987psAverage0.0000000000000sPeriods13.339000kMeasurements2.588580000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(5per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(5per) Rising Edge Measurements
Pass Limits:[-188ps to 188ps]terr5per Rising96ps

Result Details:

Result Details
Min-85.819psMax96.427psAbs. Diff182.246psAverage0.0000000000000sPeriods13.339000kMeasurements2.575440000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(6per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(6per) Rising Edge Measurements
Pass Limits:[-200ps to 200ps]terr6per Rising-105ps

Result Details:

Result Details
Min-105.482psMax99.522psAbs. Diff205.004psAverage0.0000000000000sPeriods13.339000kMeasurements2.562300000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(7per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(7per) Rising Edge Measurements
Pass Limits:[-209ps to 209ps]terr7per Rising-106ps

Result Details:

Result Details
Min-106.148psMax86.267psAbs. Diff192.415psAverage0.0000000000000sPeriods13.339000kMeasurements2.549160000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(8per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(8per) Rising Edge Measurements
Pass Limits:[-217ps to 217ps]terr8per Rising107ps

Result Details:

Result Details
Min-86.853psMax106.754psAbs. Diff193.607psAverage0.0000000000000sPeriods13.339000kMeasurements2.536020000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(9per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(9per) Rising Edge Measurements
Pass Limits:[-224ps to 224ps]terr9per Rising103ps

Result Details:

Result Details
Min-101.166psMax103.113psAbs. Diff204.279psAverage0.0000000000000sPeriods13.339000kMeasurements2.522880000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(10per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(10per) Rising Edge Measurements
Pass Limits:[-231ps to 231ps]terr10per Rising-115ps

Result Details:

Result Details
Min-115.393psMax110.150psAbs. Diff225.544psAverage0.0000000000000sPeriods13.339000kMeasurements2.509740000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(11per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(11per) Rising Edge Measurements
Pass Limits:[-237ps to 237ps]terr11per Rising-108ps

Result Details:

Result Details
Min-107.553psMax94.647psAbs. Diff202.200psAverage0.0000000000000sPeriods13.339000kMeasurements2.496600000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(12per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: terr(12per) Rising Edge Measurements
Pass Limits:[-242ps to 242ps]terr12per Rising112ps

Result Details:

Result Details
Min-95.480psMax111.722psAbs. Diff207.202psAverage0.0000000000000sPeriods13.339000kMeasurements2.483460000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(nper) Rising Edge Measurements Reference: N/A

Test Summary: Pass Test Description: terr(nper) Rising Edge Measurements
Pass Limits:[-99.000000000000E36s to 99.000000000000E36s]terrnper Rising131ps

Result Details:

Result Details
Worst Subwindow size41.000Min-135.257psMax131.079psAbs. Diff266.336psAverage0.0000000000000sPeriods13.339000kMeasurements84.634740000MWaveform SrcChannel 1nper_min13nper_max50tWorstCaseN/A

Next

tCH Average High Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tCH Average High Measurements
Pass Limits:[470.000000000mtCK(avg) to 530.000000000mtCK(avg)]tC High Pulse DC496.808959862mtCK(avg)

Result Details:

Result Details
Min497mtCK(avg)Max499mtCK(avg)Abs. Diff2mtCK(avg)Average498mtCK(avg)Periods13.340000kMeasurements13.140000ktWorstCaseN/AWaveform SrcChannel 1

Next

tCL Average Low Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tCL Average LowMeasurements
Pass Limits:[470.000000000mtCK(avg) to 530.000000000mtCK(avg)]tC Low Pulse DC503.241953452mtCK(avg)

Result Details:

Result Details
Min501mtCK(avg)Max503mtCK(avg)Abs. Diff2mtCK(avg)Average502mtCK(avg)Periods13.340000kMeasurements13.140000ktWorstCaseN/AWaveform SrcChannel 1

Next

tjit(duty-high) Jitter Average High Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tjit(duty-high) Jitter Average High Measurements
Pass Limits:[-99.000000000000E36s to 99.000000000000E36s]tjit Duty High60ps

Result Details:

Result Details
Min-51.240psMax60.388psAbs. Diff111.628psAverage-3ysPeriods13.340000kMeasurements2.628200000MWaveform SrcChannel 1tWorstCaseN/A

Next

tjit(duty-low) Jitter Average Low Measurements Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tjitduty-low Jitter Average LowMeasurements
Pass Limits:[-99.000000000000E36s to 99.000000000000E36s]tjit Duty Low60ps

Result Details:

Result Details
Min-43.531psMax60.416psAbs. Diff103.947psAverage-3ysPeriods13.340000kMeasurements2.628200000MWaveform SrcChannel 1tWorstCaseN/A

Next

tCH(abs) Absolute clock HIGH pulse width Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tCH(abs) Absolute clock HIGH pulse width
Pass Limits:>= 430.000000000mtCK(avg)tCH(abs)469.962826865mtCK(avg)

Result Details:

Result Details
Min469.962826865mtCK(avg)Max529.412109802mtCK(avg)Abs. Diff59.448749606669mtCK(avg)Average497.610679410mtCK(avg)Pulses13.340000kMeasurements13.340000kWaveform SrcChannel 1

Next

tCL(abs) Absolute clock LOW pulse width Reference: JEDEC Standard No. 79-3F, Table 68

Test Summary: Pass Test Description: tCL(abs) Absolute clock LOW pulse width
Pass Limits:>= 430.000000000mtCK(avg)tCL(abs)479.454509576mtCK(avg)

Result Details:

Result Details
Min479.454509576mtCK(avg)Max534.114484723mtCK(avg)Abs. Diff54.660508477288mtCK(avg)Average502.388787260mtCK(avg)Pulses13.340000kMeasurements13.340000kWaveform SrcChannel 1

Test Configuration Details
Device Description
LPDDR3	No
DDR3L	No
Test Mode	Compliance
Speed Grade	DDR3-1066
Test Session Details
Infiniium SW Version	04.20.0005
Infiniium Model Number	MSO9254A
Infiniium Serial Number	MY52370104
Application SW Version	2.03
Debug Mode Used	No
Compliance Limits (official)	DDR3-1066 Test Limit
Last Test Date	2013-08-21 09:43:08 UTC -06:00

Test Statistics
Failed	5
Passed	68
Total	73

Margin Thresholds
Warning	< 2 %
Critical	< 0 %

Pass	# Failed	# Trials	Test Name	Actual Value	Margin	Pass Limits
	0	1	VIH.DQ(AC)	926.805100000mV	0.2 %	VALUE >= VrefDQ_Volt+AcLevels_DQ_VoltV
	0	1	VIH.DQ(DC)	926.805100000mV	11.8 %	VrefDQ_Volt+DcLevels_VoltV <= VALUE <= VDD_VoltV
	0	1	VIL.DQ(AC)	563.000600000mV	2.1 %	VALUE <= VrefDQ_Volt-AcLevels_DQ_VoltV
	0	1	VIL.DQ(DC)	563.000600000mV	13.4 %	0.000000000000V <= VALUE <= VrefDQ_Volt-DcLevels_VoltV
	1	1	VSEH(Strobe)	-9.0000000000000E36V	-973E+36 %	VALUE >= VDD_Volt/2 + 0.175V
	1	1	VSEL(Strobe)	9.0000000000000E36V	-157E+37 %	VALUE <= VDD_Volt/2 - 0.175V
	0	1	VSEH(Clock)	1.108940000000V	19.9 %	VALUE >= VDD_Volt/2 + 0.175V
	0	1	VSEL(Clock)	-1.029060000000V	279.0 %	VALUE <= VDD_Volt/2 - 0.175V
	0	1	VOH(AC)	1.241860000000V	38.0 %	VALUE >= VTT_Volt+0.1*VDDQ_VoltV
	0	1	VOH(DC)	1.241860000000V	3.5 %	VALUE >= 0.8*VDDQ_VoltV
	0	1	VOL(AC)	294.670000000mV	50.9 %	VALUE <= VTT_Volt-0.1*VDDQ_VoltV
	0	1	VOL(DC)	294.670000000mV	1.8 %	VALUE <= 0.2*VDDQ_VoltV
	0	1	SRQseR	2.892874000000V/ns	15.7 %	2.500000000000V/ns <= VALUE <= 5.000000000000V/ns
	0	1	SRQseF	2.940383000000V/ns	17.6 %	2.500000000000V/ns <= VALUE <= 5.000000000000V/ns
	0	1	Overshoot amplitude (Clock, Data, Strobe, Mask)	-204.600000000mV	151.2 %	VALUE <= 400.000000000mV
	0	1	Overshoot area (Clock, Data, Strobe, Mask)	0.000000000000V-ns	100.0 %	VALUE <= 190.000000000mV-ns
	0	1	Undershoot amplitude (Clock, Data, Strobe, Mask)	-258.790000000mV	164.7 %	VALUE <= 400.000000000mV
	0	1	Undershoot area (Clock, Data, Strobe, Mask)	0.000000000000V-ns	100.0 %	VALUE <= 190.000000000mV-ns
	0	1	VIHdiff.CK(AC)	481.750000000mV	37.6 %	VALUE >= 2*(VIHAC_CA_Volt-VrefCA_Volt)V
	0	1	VILdiff.CK(AC)	-544.580000000mV	55.6 %	VALUE <= 2*(VILAC_CA_Volt-VrefCA_Volt)V
	0	1	VIHdiff.DQS(AC)	452.890000000mV	29.4 %	VALUE >= 2*(VIHAC_DQ_Volt-VrefDQ_Volt)V
	0	1	VILdiff.DQS(AC)	-401.460000000mV	14.7 %	VALUE <= 2*(VILAC_DQ_Volt-VrefDQ_Volt)V
	1	1	VIX	9.0000000000000E36V	-300E+37 %	-150.000000000mV <= VALUE <= 150.000000000mV
	0	1	VOHdiff(AC)	779.910000000mV	160.0 %	VALUE >= 0.2*VDDQ_VoltV
	0	1	VOLdiff(AC)	-779.740000000mV	159.9 %	VALUE <= -0.2*VDDQ_VoltV
	0	1	SRQdiffR	5.090149000000V/ns	1.8 %	5.000000000000V/ns <= VALUE <= 10.000000000000V/ns
	0	1	SRQdiffF	5.235437000000V/ns	4.7 %	5.000000000000V/ns <= VALUE <= 10.000000000000V/ns
	0	1	tDS(base)	330ps	122E+01 %	VALUE >= tDS_Limit_mins
	0	1	tDH(base)	380ps	280.0 %	VALUE >= tDH_Limit_mins
	0	1	tDS-Diff(derate)	330ps	205.6 %	VALUE >= tDSDiff_DeratedLimit_Mins
	0	1	tDH-Diff(derate)	380ps	280.0 %	VALUE >= tDHDiff_DeratedLimit_Mins
	0	1	tDIPW	892ps	82.0 %	VALUE >= 490ps
	0	1	tVAC(Data)	721.1ps		Information Only
	0	1	tWPRE	1.139028000000tCK	26.6 %	VALUE >= 900.000000000mtCK
	0	1	tWPST	434.4140000000mtCK	44.8 %	VALUE >= 300.0000000000mtCK
	0	1	tDQSS	89.875980000mtCK	32.0 %	-250.000000000mtCK <= VALUE <= 250.000000000mtCK
	0	1	tDSS	535.684800000mtCK	167.8 %	VALUE >= 200.000000000mtCK
	0	1	tDSH	411.053700000mtCK	105.5 %	VALUE >= 200.000000000mtCK
	0	1	tDQSL	493.697600000mtCK	43.7 %	450.000000000mtCK <= VALUE <= 550.000000000mtCK
	0	1	tDQSH	505.511600000mtCK	44.5 %	450.000000000mtCK <= VALUE <= 550.000000000mtCK
	0	1	tDQSQ	45ps	70.0 %	VALUE <= 150ps
	0	1	tQH	467.170200000mtCK	22.9 %	VALUE >= 380.000000000mtCK
	0	1	tLZDQ	73.3ps	25.2 %	-600.0ps <= VALUE <= 300.0ps
	0	1	tHZDQ	111.7ps	62.8 %	VALUE <= 300.0ps
	0	1	tRPRE	1.133045000000tCK	40.2 %	900.000000000mtCK <= VALUE <= 1.480000000000tCK
	0	1	tRPST	424.7213000000mtCK	19.5 %	300.0000000000mtCK <= VALUE <= 940.0000000000mtCK
	0	1	tDQSCK	251ps	8.2 %	-300ps <= VALUE <= 300ps
	0	1	tDVAC(Clock)	349.9ps		Information Only
	0	1	tLZDQS	8.9ps	32.3 %	-600.0ps <= VALUE <= 300.0ps
	0	1	tQSH	488.9755000000mtCK	28.7 %	VALUE >= 380.0000000000mtCK
	0	1	tQSL	472.4601000000mtCK	24.3 %	VALUE >= 380.0000000000mtCK
	0	1	tDVAC(Strobe)	746.9ps		Information Only
	0	1	tjit(CC) Rising Edge Measurements	-141ps	10.8 %	-180ps <= VALUE <= 180ps
	1	1	tCK(avg) Rising Edge Measurements	1.874ns	-0.2 %	1.875ns <= VALUE <= 2.500ns
	1	1	tjit(per) Rising Edge Measurements	92ps	-1.1 %	-90ps <= VALUE <= 90ps
	0	1	terr(2per) Rising Edge Measurements	-91ps	15.5 %	-132ps <= VALUE <= 132ps
	0	1	terr(3per) Rising Edge Measurements	-98ps	18.8 %	-157ps <= VALUE <= 157ps
	0	1	terr(4per) Rising Edge Measurements	-84ps	26.0 %	-175ps <= VALUE <= 175ps
	0	1	terr(5per) Rising Edge Measurements	96ps	24.5 %	-188ps <= VALUE <= 188ps
	0	1	terr(6per) Rising Edge Measurements	-105ps	23.8 %	-200ps <= VALUE <= 200ps
	0	1	terr(7per) Rising Edge Measurements	-106ps	24.6 %	-209ps <= VALUE <= 209ps
	0	1	terr(8per) Rising Edge Measurements	107ps	25.3 %	-217ps <= VALUE <= 217ps
	0	1	terr(9per) Rising Edge Measurements	103ps	27.0 %	-224ps <= VALUE <= 224ps
	0	1	terr(10per) Rising Edge Measurements	-115ps	25.1 %	-231ps <= VALUE <= 231ps
	0	1	terr(11per) Rising Edge Measurements	-108ps	27.2 %	-237ps <= VALUE <= 237ps
	0	1	terr(12per) Rising Edge Measurements	112ps	26.9 %	-242ps <= VALUE <= 242ps
	0	1	terr(nper) Rising Edge Measurements	131ps	50.0 %	-99.000000000000E36s <= VALUE <= 99.000000000000E36s
	0	1	tCH Average High Measurements	496.808959862mtCK(avg)	44.7 %	470.000000000mtCK(avg) <= VALUE <= 530.000000000mtCK(avg)
	0	1	tCL Average Low Measurements	503.241953452mtCK(avg)	44.6 %	470.000000000mtCK(avg) <= VALUE <= 530.000000000mtCK(avg)
	0	1	tjit(duty-high) Jitter Average High Measurements	60ps	50.0 %	-99.000000000000E36s <= VALUE <= 99.000000000000E36s
	0	1	tjit(duty-low) Jitter Average Low Measurements	60ps	50.0 %	-99.000000000000E36s <= VALUE <= 99.000000000000E36s
	0	1	tCH(abs) Absolute clock HIGH pulse width	469.962826865mtCK(avg)	9.3 %	VALUE >= 430.000000000mtCK(avg)
	0	1	tCL(abs) Absolute clock LOW pulse width	479.454509576mtCK(avg)	11.5 %	VALUE >= 430.000000000mtCK(avg)

Summary of Results

Report Detail